1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device wherein various potentials, including at least one potential either raised or lowered, are assigned to circuit blocks, and also to a method of screening this semiconductor device.
2. Description of the Related Art
Semiconductor devices are subjected to a test generally known as "screening" before they are shipped from the factory to users. The purpose of the screening is to find devices having defects which may eventually render the devices useless or malfunctioning, and discard these defective semiconductor devices. The known method of screening is to apply a voltage to the semiconductor devices, said voltage being higher than the driving voltage of the devices, for a time much shorter than the period during which the device may have troubles for the first time. Hence, the devices have, within a short time, the stress which would have been imposed on them if they were operated at their driving voltage a little longer than said period. Those of the devices which have troubles are discarded, and only the remaining reliable semiconductor devices are delivered to the users.
Hitherto, packaged DRAMs (Dynamic Random-Access Memories) are screened by supplying address signals to their address input terminals, thereby accessing their word lines. This screening method is not efficient, in particular for checking the transfer gates of the memory cells of each DRAM.
In order to increase the screening efficiency, the inventors hereof invented the DRAM disclosed in U.S. patent application Ser. No. 544,614, which is so designed that a voltage stress can be applied to all word lines, or the word lines, the member of which is more than that of ward lines selected for normal operation, at the same time. This DRAM can be screened before it is cut from a wafer. In other words, the identical DRAM chips formed on the same wafer can be screened within a short time by means of a prober and a probe card.
As is commonly practiced in the art, a raised voltage is applied to the word lines connected to the transfer gates of DRAM memory cells, so that a voltage as high as the power-supply potential of the DRAM to the memory nodes of the memory cells. More specifically, in a 4-Mbit DRAM or a DRAM having less storage capacity, a potential higher than the the power-supply potential, which is the raised voltage, is applied to the word lines, while the power-supply potential is externally applied directly to most circuit blocks of the DRAM. In the case of a 16-Mbit DRAM, most circuit blocks are driven with an internal lowered power-supply voltage, and the word lines are driven with a raised internal power-supply potential, as is disclosed in M. Horiguchi et al., DualOperating-Voltage Scheme for a Single 5 V, 16-Mbit DRAM, IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, Oct. 1988, pp. 1128-1132. Alternatively, in a 16-Mbit DRAM, most circuit blocks are driven with an internal lowered power-supply voltage, and the word lines are driven with an external power-supply potential, as is disclosed in T. Takeshima et al., A 55 ns 16 Mb DRAM, ISSCC 89, pp. 246-247.
In most DRAMs, the MOS transistors used as the transfer gates of the memory cells, and the MOS transistors incorporated in the circuits peripheral to the memory cells have gate insulation layers of the same thickness. Hence, if the potential applied to the word lines is higher than the potential applied to the other elements of the DRAM, a greater voltage stress is imposed on the MOS transistors used as transfer gates than on the other MOS transistors. In the case of a DRAM driven with the externally applied power-supply potential Vcc, a voltage as high as 1.5 Vcc is applied to the word lines. When the DRAM is subjected to screening performed at 7 V, the potential of the word lines will amount to 10.5 V. Assuming that the transfer gates of the memory cells have a thickness of 200 .ANG., the electric field applied to the transfer gates will have an intensity of more than 5 MV/cm.
The voltage that can be applied to screen DRAMs must be low enough not to break down the transfer gates of the memory cells to which the raised voltage is applied, or not to cause the junction breakdown of the diffusion layer to which the raised voltage is applied. When such a relatively low screening voltage is applied to a DRAM, an insufficiently intense electric field is applied to the elements other than the transfer gates and the diffusion layer. Consequently, the potential defects of the DRAM, if any, cannot be detected within a short period of time. In other words, it is necessary to carry out the screening on a DRAM for a long time in order to detect the defects, if at least one of the various potential assigned to circuit blocks of the DRAM is either raised or lowered internally.